someone on here posted jokingly about how everyone has a pet RISC-V implementation and I needed a little project to make sure my brain was fully in verilog mode while waiting for my amiga parts to show up / before attempting to implement something that doesn't have a great specification, so I decided to work on a RISC-V implementation for the past few days and it just successfully ran the first instruction of rv32ui-p-simple (j pc+0x48) from the RISC-V test suite
next up: getting csrr a0, mhartid to work