I have uploaded Amaranth HDL code that creates parametric, pipelined signed and unsigned integer multipliers. They can do one multiply every clock cycle after an initial latency proportional to the input operands width.
Last I checked, a lone 8x8-bit unsigned multiplier could do 70MHz on even the slow-ass ICE40UP5K. However, I've since removed the code that made it easy to benchmark Fmax and resource usage, to be re-integrated at a later date.
At least for an 8x8 multiplier, I've tested all 65536 possible multiplies and both unsigned and signed multipliers pass. They are also commented on how they work (I hope well). However, if your FPGA has hard IP for multipliers, like most Xilinx offerrings, you probably don't want to use this repo, as the number of LUTs and FFs required grows quadratically with the multiplier size (IIRC, ~300 LUTs/FFs for 8-by-8, 1200 LUTs for 16-by-16, etc).