This evening I've been playing around some more with Amaranth HDL, writing some code for the little FPGA on the right. I wanted to have a communication channel with the RP2040 on the left.
So I wrote an UART transmit module. It sends out a byte one bit at a time with a fixed time interval, which the other side can sample at the same times.
Initially the bugs were in the python code itself, but then I got to the logic and timing bugs. I transmitted one bit too many, and I didn't reset the timer after the start bit. Luckily Amaranth has a good simulator and I could see those issues after setting that up.
It was nice to experience that I could still make something for a FPGA, and it gives me the confidence to try something more complicated.